ARM Processor is a key component for many successful and widely used 32 – bit embedded systems. ARM Processors are widely used in mobile phones, PDAs, and many other portable consumer devices. ARM is based on RISC (Reduced Instruction Set Computer) design philosophy which makes it a flexible yet powerful processor core with minimal power requirements, thus the ideal choice for an embedded system.
The RISC Design Philosophy
RISC aims at delivering simple but powerful instructions that can be executed in a single clock cycle. The hardware complexity is reduced at the cost of increasing complexity in the software. Major design rules are:
- Instructions: RISC processors have a smaller instruction set with simple instructions that can be executed in a single clock cycle. The complex instructions are synthesized by complier by combining several simple instructions. This reduces complexity in the hardware.
- Pipelines: The processing of instructions is broken into small units that can be executed in parallel, e.g. the processor can execute some instruction of one process while the memory controller is fetching instruction of the other process. Thus the processor executes for the maximum time and processor utilization is increased.
- Registers: RISC machines have large general purpose register set and any register can contain data or address. They act as fast local memory for all data.
- Load – Store Architecture: The processor can operate on data held in registers only. Separate load and store operations are used to transfer data from register to external memory and vice versa. This speeds up the operations as processor access registers only while operations instead of costly memory access.
The ARM Design
ARM is essentially based on the RISC design philosophy but it does not completely follow the RISC design. Many deviations from the RISC design are taken to make the ARM more suited for embedded systems. The deviations are:
- Variable cycle execution for certain instructions – Certain ARM instructions take more than one cycle to execute. E.g. Load and Store instructions vary in the number of cycles depending on the number of registers being transferred.
- Inline barrel shifter leading to more complex instructions – The inline barrel shifter is a hardware component that preprocesses one of the registers before it is used by an instruction. This expands the capability of many instructions to improve core performance and code density.
- Thumb 16 – bit instruction set – It permits the ARM processor to execute 16 bits instructions as well.
- Conditional execution – An instruction is executed only if a specific condition is achieved, this improves performance and reduces branch instructions.
- Enhanced instructions – ARM processors support enhanced DSP instructions for various digital signal operations.
A programmer can think of ARM core as functional units e.g. ALU, MMU, etc connected by data buses. Data enters the processor through the data bus, the data may be an instruction or a data item itself. The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set. Like all RISC machines ARM uses Load and Store instructions to transfer data in and out of the processor as ARM can ONLY work on the data in registers. So the data has to be moved to registers before any operation. The ALU takes data from the registers and performs the required operations and finally saves back to the register, from where the result can be written back to external memory using a store operation.
An ARM processor has upto 18 active registers : 16 data and 2 process registers. All are 32 bits in size, named as r0 to r15. The registers r13, r14, and r15 are used for some specific tasks, r13 is used as Stack Pointer, r14 is used as link register and r15 is used as program counter, depending on the context these registers can also be used as general purpose registers. There are two program registers also named as cpsr and spsr (Current program status and saved program status register) used to store the processor and the program status.